1. Field of the Invention
This invention relates to a communication system comprising a network of interconnected transceivers, encoders and decoders. The encoders can produce a bitstream encoded at the same rate as the source data and, over time, incurs no DC accumulation. The encoded bitstream can be wrapped within a packet or frame with a preamble having a coding violation used not only to synchronize a decoder but also to detect transmission errors.
2. Description of the Related Art
Communication systems are generally well known as containing at least two nodes interconnected by a communication line. Each node may include both a transmitter and a receiver, generally referred to as a xe2x80x9ctransceiver.xe2x80x9d The transceiver provides an interface between signals sent over a communication line and a digital system which operates upon that signal in the digital domain.
FIG. 1 illustrates a set of nodes 10 interconnected by one or more communication lines, to form a communication system or network 12. The network topography or backbone can vary depending on its application. The signal transmitted across the network can contain instructions and/or data, which conceivably could be audio data, video data, or both and, therefore, the network can be considered a multi-media network. The transfer rate of multi-media signals may be generally quite high and may require a relatively high speed communication line, a suitable line being an optical fiber, for example.
If an optical fiber is used, then the receiver portion of the transceiver converts light energy to an electrical signal. FIG. 2 illustrates a transmitter portion 14 of a transceiver linked by a communication line 16 to a receiver portion 18 of another transceiver. Transmitter 14 includes a light emitting diode (xe2x80x9cLEDxe2x80x9d) 20 that converts electrical signals to optical or light energy forwarded across communication line 16. At a node remote from transmitter 14, receiver 18 includes a photosensor 22.
The load capacitance of LED 20 may require a substantial amount of drive current from amplifier 24. The higher the bit rate, the more current need be driven to LED 20. Likewise, the higher the transmitted bit rate, the greater the electromagnetic (xe2x80x9cEMxe2x80x9d) radiation at both the transmitter 14 and receiver 18.
The data transmitted across communication line 16 is generally encoded and placed within a packet or frame. A need exists for transferring data at a high bit rate; however, it is important that the overhead needed to encode that data be substantially minimized. In other words, if encoding were to add unnecessary transitions in the transferred data, then impermissibly high drive current is needed to more quickly transition LED 20. The speed by which LED 20 can transition is limited by the capacity of components within transmitter 14, and also the EM radiated by transmitter 14.
FIG. 3 illustrates an incoming bitstream of source data, and the resulting encoding of that source data. Encoding is shown according to either a biphase code or a Miller code, both of which are fairly popular coding mechanisms. The source data maximum transmission rate (defined as the minimum source data cycle) is limited to two clock cycles. In other words, each high or low pulse of the source data is equal to or greater than one clock cycle. The biphase coding scheme, however, requires that for each logic high value of source data, a transition occurs at the middle as well as boundary regions of that clock phase. The biphase coding scheme thereby encodes the data rate at twice the source data rate whenever the source data encounters a logic high value. This significantly reduces the available bandwidth of the transmission line and, as described above, the current draw and EM radiation of the transmitter will significantly increase.
FIG. 3 also illustrates the Miller coding scheme. Miller coding has one distinct advantage over biphase coding in that the encoded data rate is not twice the source data rate. The Miller encoded data rate is designed to be the same as the source data rate to enhance the total available bandwidth of the transmission line and reduce the burdens upon the components of the transmitter and receiver. In Miller coding, a logic high value is encoded by a transition at the center or middle of a clock phase, while logic low voltage values are encoded by transitions at the boundary of a clock phase. The minimum distance between transitions of neighboring logic low and high voltage values is, however, maintained at one clock phase or clock cycle.
An unfortunate aspect of Miller coding is that the encoded bitstream incurs an accumulated DC value. As shown in FIG. 3, a logic low voltage value for the duration of one clock phase represents a negative DC value (xe2x80x9cxe2x88x921xe2x80x9d), and a logic high voltage value during a clock phase represents a positive DC voltage value (xe2x80x9c+1xe2x80x9d). It is desirable that the accumulated DC voltage value be at the median between logic high and logic low voltage values. On line 26, the cumulative DC voltage value, also know as the digital sum value (or xe2x80x9cDSVxe2x80x9d) is shown for the Miller coding. A transition at the middle of a clock cycle or phase represents no change in DC voltage value (xe2x80x9c0xe2x80x9d) thereby not adding to or taking away from the DSV. DSV indicates the Miller coding becomes more and more skewed towards the logic low voltage value, as indicated by a xe2x88x923 DSV for the source data shown.
Referring to FIGS. 2 and 3 in combination, a skewed DC value from a voltage at the midline between logic high and logic low voltage values (i.e., a DSV greater than or less than 0) will accumulate upon capacitor 28 and the input node of comparator 30. Accumulation of a DC value or xe2x80x9coffsetxe2x80x9d will cause what is known as baseline wander, which causes receiver 18 to detect an encoded signal which is dependent upon the bit sequence of that signal. Detection is no longer based on an ideal DC-free coding signal, but instead, wanders from the baseline or midline voltage value.
It would be beneficial to introduce an encoder and coding methodology that avoids coding at a higher rate than the incoming source data, but without introducing unduly large, cumulative DC voltage. The improved encoder is therefore one which produces minimal DC skew for relatively short periods of time, and over a more lengthy time period, produces no DC skew whatsoever. The desired DC skew can occur only for short durations which would advantageously be less than the RC time constant of resistor 32 and capacitor 28, shown in FIG. 2 as a low-pass filter at the input of comparator 30. The desired encoder and encoding methodology can be used in any communication system employing transmitters and receivers and, while beneficially used in an optical transmission system, the improved encoder and methodology can be used to transmit signals over copper wire or through an air (optical or acoustic) medium, for example.
The problems outlined are in large part solved by an improved encoder, communication system, and methodology thereof. The communication system is one which can forward multi-media signals across airwaves, copper wire, and/or fiber optic cables. The coding mechanism is chosen to forward the coded bitstream at a rate not to exceed the source data, and the encoded data is substantially DC-free. In many instances, the times in which the encoded data is not DC-free can be relatively short, and assuredly shorter than the RC time constant of the receiver, regardless of the form of that receiver.
The DC-free encoded bitstream is henceforth referenced as a DC-adaptive bitstream or xe2x80x9cDCAxe2x80x9d bitstream. The encoded DCA bitstream is partially based on the DSV of the previous clock cycle, which is the cumulative DC value of the encoded DCA bitstream cumulative through the previous clock cycle. The DSV is guaranteed by the encoder to not exceed +1 or be less than xe2x88x921, and therefore is always equal to +1, 0, or xe2x88x921.
To encode, knowledge is needed of the cumulative DC value (xe2x80x9cDSVxe2x80x9d) up to and including the previous clock cycle (DSVnxe2x88x921), the logic voltage value of the source data for the current clock cycle (bitn), and the logic value of the source data for the following clock cycle (bitn+1). Depending on those values and/or logic states, the encoder can make a determination on whether it is to operate under a normal encoding state or a multiple-one encoding state.
When operating under the normal encoding state, the encoder will encode a logic high voltage value by transitioning the encoded signal at substantially the middle of the clock cycle. To encode a logic low voltage value, there will be no transitions in the middle of the clock cycle and instead will cause transitions at the beginning or end (i.e., boundary) of the clock cycle, depending on the whereabouts of the preceding or successive encoded transitions. Thus, an encoded logic low value will cause a transition at a clock cycle boundary (i.e., between cycle nxe2x88x921 and n and/or between clock cycle n and n+1), unless there is a middle transition in the encoded signal in a clock cycle immediately before or after the present clock cycle boundary. DSV will be incremented or decremented according to the DC value of the DCA encoded bitstream. A DSV of a clock cycle with a middle transition is the same as the DSV of the previous clock cycle. That is, no DC value accrues for a middle transition.
Multiple-one encoding occurs under two circumstances. If the DSV of the previous clock cycle (DSVnxe2x88x921) is non-zero and the current and next clocking cycles (n, n+1) encounter a pair of logic high voltage values, then a transition will occur at the beginning of the current clock cycle n and no transitions will occur between clock cycle n and clock cycle n+1.
By ensuring a transition at the beginning of clock cycle n and not in the middle of clock cycle n, the DC value during clock cycle n will not to be zero, but instead will offset DSVnxe2x88x921. In this manner, coding multiple-ones (i.e., multiple logic high values) will not further skew the DSV outside of a tolerable range. More importantly, the relatively short DC skews will be less than the RC time constant of the receiver so as to essentially produce a DC-free encoded signal when viewed from the perspective of the detector""s low-pass filter. The detector can therefore enjoy the benefits of non-detectable baseline wander as well as an encoded bitstream that has the same data rate as the source data. The multiple-one encoding mechanism is adaptably employed based on the DSVnxe2x88x921 and the present and successive source data bits (bitn and bitn+1).
According to one embodiment, an encoder is presented. The encoder can be adapted to encode a logic high voltage value that occurs during an n clock cycle by producing a transition near the beginning of the n clock cycle, provided a logic high voltage value occurs during an n+1 clock cycle and the sum of DC voltage values of all encoded logic high and low voltage values is skewed toward either a logic high or low voltage value prior to the n clock cycle. The sum thusly described is referenced as DSVnxe2x88x921.
When not operating in a multiple-one encoding scheme, the encoder can encode logic high voltage values by producing transitions near the middle of clock cycle n during which the logic high voltage value occurs. Transitions near the middle of n clock cycle may occur if the encoder does not encounter multiple-one voltage values circumstances of the incoming bitstream. Therefore, a transition near the middle of the n clock cycle may occur if a logic low voltage value occurs during the n+1 clock cycle or the DC voltage value of clock cycle nxe2x88x921 (DSVnxe2x88x921) is not skewed.
An erroneous transition that does not meet the aforesaid rules can be purposely placed near the middle of n clock cycle, or at the boundary between n and n+1 clock cycles to signal a coding violation. The erroneous transition may be produced near the middle or end of the n clock cycle (between the n clock cycle and the n+1 clock cycle) if a logic high voltage value occurs during the n and n+1 clock cycles and DSVnxe2x88x921 is skewed. Alternatively, not producing a transition where it should be have validly placed can also cause a coding violation. In whatever form, whether a missing, valid transition or an erroneous transition, the coding violation serves to synchronize a decoder. The erroneous transition or missing, valid transition can occur within a preamble of a packet or frame of data to signal the beginning of an encoded sequence of the DCA bitstream.
According to a further embodiment, a communication system is presented. The communication system includes an encoder that is linked to a decoder by a transmission line. The encoder is coupled to produce an encoded bitstream of data interposed in time between a first preamble and a second preamble. The first preamble can be encoded with a first DC voltage value (i.e., first DSV cumulative to the end of the first preamble), and the second preamble can be encoded with a second DC voltage value (i.e., a second DSV cumulative to the end of the second preamble). The decoder can receive a first and second preamble and compares the first DC voltage value with the second DC voltage value to determine if an error occurred during transmission of the encoded bitstream across the transmission line. The first and second DC voltage values can be the same or dissimilar. For example, an adder may be used to determine if the sum of the first DC voltage value and the second DC voltage value is skewed from a midline voltage. In this instance, the first DC voltage value can be 0 and the second DC voltage value can be 0, whereby the adder should produce an added DC voltage value of 0. Alternatively, but not exclusively, a comparator may be used to determine if either the first DC voltage value or the second DC voltage value is dissimilar from 0, +1 or xe2x88x921, depending on the chosen DC voltage values. If the DC voltage value is something other than what is expected, then it is known that an error occurred in transmission between the time of the first preamble and the second preamble. According to yet another error detection methodology, it is known that the DSV of the encoded bitstream must remain between xe2x88x921 and +1. If the DSV exceeds +1 (i.e., +2) or is less than xe2x88x921 (i.e., xe2x88x922), then it is known that an error occurred during transmission. The error can be pinpointed to the frame or packet at which at out-of-range condition occurs.
The decoder can be synchronized using various mechanisms, examples of which are the detection of a misplaced or erroneous transition, or the detection of an encoded pulse which was, for example, longer than the longest allowable pulse. The same can apply in the detection of a cycle longer than or shorter than the longest or shortest allowable encoded cycle. Once the decoder detects a coding violation, the decoder can be synchronized as to where the bit-boundary occurs to prevent decoding, for example, a xe2x80x9c0000xe2x80x9d bitstream instead of a xe2x80x9c1111xe2x80x9d bitstream.
According to yet another embodiment, a method is described for encoding a bitstream of logic low and logic high voltage values. The method includes the steps of computing a sum of DC voltage values for all encoded logic low and logic high voltage values prior to an n clocking cycle (i.e., DSVnxe2x88x921). A logic high voltage value can be detected within the bitstream during the n clock cycle and an n+1 clock cycle. Thereafter, a transition is produced within an encoded bitstream near the beginning of n clock cycle and not between clock cycles n and n+1, provided the DSVnxe2x88x921 is skewed toward either the logic high or logic low voltage values and a logic high voltage value for the source data has been detected during clock cycles n and n+1.